1. Field of the Invention
The present invention relates to an improvement in a priority encoder formed in a semiconductor integrated circuit and, more particularly, to a priority encoder used for a device, in a microprocessor, such as a multiplier or a frame switching system for image processing.
2. Description of the Related Art
In a microprocessor or a peripheral interface apparatus having a timer function, a serial interface function, a parallel interface function, and the like, instructions and data are often coded to be used. A priority encoder having a bit priority function with respect to an input signal is widely used for a multiplier, a frame switching system for image processing, or the like in a microprocessor.
N-bit data can be easily coded by logical 0R operations. More specifically, an operation function, of an upper bit priority type 8-bit encoder, indicated by a truth table shown in FIG. 1, can be realized by a static logic circuit shown in FIG. 2. FIG. 1 shows a relationship between 8-bit code inputs D.sub.7 (most significant bit: MSB) to D.sub.0 (least significant bit: MSB), an enable control input Ei, and output signals GS, E.sub.O, QA, QB, and QC. A symbol * indicates a Low Level or high level (don't care). Referring to FIG. 2, reference numerals 71 to 77 denote NAND gates; 78 to 89, NOR gates; 90 to 93, inverters; and 94 and 95, AND gates.
In the static circuit arrangement shown in FIG. 2, however, a large number of logic circuits are required to check the state of each signal and to detect and code an active MSB signal. In addition, as the number of bits of an input signal is increased from 8 bits to 10 bits, 16 bits, and 32 bits, hardware for detecting an active MSB signal becomes considerably complicated. Furthermore, the number of elements is increased to several times to several tens times what it was, and the proportion of an area occupied by the encoder to the total area on an IC chip is increased.
Moreover, in the conventional priority encoder, a priority direction is fixed. For this reason, in order to realize a lower bit priority type encoder, the input terminals of an upper bit priority type encoder must be reversed. That is, the above-described upper bit priority type 8-bit encoder must be switched to be also used as a lower bit priority type encoder. As shown in FIG. 3, therefore, such an arrangement requires 2-bit input terminals for respectively receiving bit pairs of an input signal: 0th bit and 7th bit, 1st bit and 6th bit, 2nd bit and 5th bit, and 3rd bit and 4th bit, and selectors SEL, corresponding to 8 bits, for selecting the respective 2-bit input terminals in accordance with a select signal Eh.
If a system is constituted by such static logic circuits as described above, the number of elements of a 10-bit priority encoder is increased to about twice that of an 8-bit priority encoder, as shown in FIG. 4. That is, the 10-bit priority encoder requires a chip area about twice that of the 8-bit priority encoder. The number of elements of a 16-bit priority encoder is increased to about four times that of the 10-bit priority encoder. That is, the 16-bit priority encoder requires a chip area about four times that of the 10-bit priority encoder. Therefore, in a high-level microcomputer having a large number of bits to be processed, the packing density is decreased, resulting in a decrease in operating speed. In other words, conventional hardware cannot satisfy the demands for higher performance and packing density.